3/30/2023 0 Comments L3 photostyler![]() And perhaps most importantly, it was three times as energy efficient as the microbump 3D approaches. ![]() What AMD did reiterate about this cache stacking technique it co-developed with TSMC was that it had more than 200X the interconnect density of on-package, 2D chiplet packaging techniques and more than 15X the interconnect density of microbump 3D packaging approaches. It is not clear how much this 3D V-Cache approach adds to the cost of a processor, but clearly it is going to be used for specific HPC and AI workloads where cache is king. With the 3D V-Cache, AMD took another 64 MB of SRAM and stacked it onto of each of the CCDs, and using a direct copper-to-copper interconnect between the SRAM on the compute die and the SRAM stacked on top of it, using through silicon vias (TSVs), and using a process that does not require microbumps or solder to make the links, AMD was able to triple the 元 cache capacity on the Ryzen 5900X prototype to 192 MB. Each CCD has 32 MB of 元 cache etched onto the chiplet, for a total of 64 MB of integrated 元 cache. The Ryzen 5900X processor comes with either 12 or 16 cores in package with two core complex dies, or CCDs as AMD calls its compute chiplets. But it has been in development for years by AMD and its foundry partner, Taiwan Semiconductor Manufacturing Co, and moreover, was always intended to be put into production first on server processors. The 3D V-Cache technique was previewed back in June by Su, in this case on a prototype using a Ryzen 5900X processor aimed at desktop PCs. And this extra 元 cache is revving up the HPC applications that it is initially targeted at, which include finite element analysis, structural analysis, computational fluid dynamics, and electronic design automation. The Milan-X has no architectural changes in the processor, and will also top out at 64 cores, but it does have lots of extra 元 cache stacked on top of the compute chiplets in the Milan package. There are lots of innovations between the Rome and Milan generations, which we talked about in our initial coverage of the Milan chips back in March we drilled down into the Milan architecture further here. ![]() The Milan server processors pack eight chiplets, with eight Zen 3 cores each, and a central I/O and memory hub to create a 64-core socket, much as the “Rome” Epyc 7002 chips did before them. Microsoft’s Azure cloud is the first to get its hands on the Milan-X chips, and has released some initial performance specs for the processor, as we report elsewhere on The Next Platform. Lisa Su, AMD president and chief executive officer, and her team previewed the Milan-X, which we presume will be a few special SKUs – probably not more than that – of the existing Epyc 7003s when they come out in the first quarter of 2022. The resulting “Milan-X” processors were previewed at AMD’s Accelerated Computing Premier online event today, which was timed to be a spoiler for Nvidia’s fall GTC 2021 conference, which starts tomorrow. And X86 server chip maker AMD is striking first with a new 3D packaging technology for 元 cache on server chips, called 3D V-Cache appropriately enough, that has been married to its current “Milan” Epyc 7003 processors and that is providing a big performance boost for HPC simulation and modeling workloads. Necessity is the mother of invention, and advances in chip packaging are catching up to those in transistor design when it comes to working in three dimensions instead of the much more limited two.
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